module mux_case (source, ce, wrclk, selector, result);
      input [3:0] source;
      input ce, wrclk;
      input [1:0] selector;
      output result;
      reg [3:0] intreg; // intreg y result_int son señales locales
      reg result, result_int;

      always @(posedge wrclk)
        begin
          if(ce)
            intreg = source;
          result = result_int;
        end

      always @(intreg or selector)
        case(selector)
          2’b00: result_int = intreg[0];
          2’b01: result_int = intreg[1];
          2’b10: result_int = intreg[2];
          2’b11: result_int = intreg[3];
        endcase
    endmodule // mux_case