// This file was generated by
// Qfsm Version 0.54
// (C) Stefan Duffner, Rainer Strobel

module FSM (clock, reset, in, state, moore);
  input     clock, reset;
  input  [3:0]  in;
  output [3:0]  moore;
  output [1:0]  state;

  reg[3:0]      moore;
  reg[1:0]      state, nextstate;

  parameter idle = 2'b00, init = 2'b01, calculate = 2'b10, done = 2'b11;

  always @ (posedge reset or posedge clock) begin
    if (reset)
      begin
        state <= idle;
        moore <= 4'b1100;
      end;
    else
      begin
        state <= nextstate;
        case (nextstate)
          idle:
            moore <= 4'b1100;
          init:
            moore <= 4'b1010;
          calculate:
            moore <= 4'b0001;
          done:
            moore <= 4'b0000;
        endcase
      end
  end

  always @ (in or state) begin
      nextstate = state;
      case (state)
        idle:
        begin
          if (in==4'b1000 ||
              in==4'b1100 ||
              in==4'b1010 ||
              in==4'b1001 ||
              in==4'b1110 ||
              in==4'b1101 ||
              in==4'b1011 ||
              in==4'b1111)
          begin
            nextstate = init;
          end
        end
        init:
        begin
          if (in==4'b0000 ||
              in==4'b1000 ||
              in==4'b0001 ||
              in==4'b1001)
          begin
            nextstate = calculate;
          end
          else if (in==4'b0010 ||
              in==4'b1010 ||
              in==4'b0110 ||
              in==4'b0011 ||
              in==4'b1110 ||
              in==4'b1011 ||
              in==4'b0111 ||
              in==4'b1111)
          begin
            nextstate = done;
          end
          else if (in==4'b0100 ||
              in==4'b1100 ||
              in==4'b0110 ||
              in==4'b0101 ||
              in==4'b1110 ||
              in==4'b1101 ||
              in==4'b0111 ||
              in==4'b1111)
          begin
            nextstate = done;
          end
        end
        calculate:
        begin
          if (in==4'b0001 ||
              in==4'b1001 ||
              in==4'b0101 ||
              in==4'b0011 ||
              in==4'b1101 ||
              in==4'b1011 ||
              in==4'b0111 ||
              in==4'b1111)
          begin
            nextstate = done;
          end
        end
        done:
        begin
          if (in==4'b0000 ||
              in==4'b0100 ||
              in==4'b0010 ||
              in==4'b0001 ||
              in==4'b0110 ||
              in==4'b0101 ||
              in==4'b0011 ||
              in==4'b0111)
          begin
            nextstate = idle;
          end
        end
      endcase
  end

endmodule