/**************************************
* Module: alu_tb
* Date:2015-11-14
* Author: usuario
*
* Description:
***************************************/
`timescale 1ns / 100ps

module  alu_tb;
    reg [15:0] A, B;
    reg [1:0] op;

    wire [15:0] result;
    wire C, Z;

    alu #(.n_bits(16)) uut (
        .A(A),
        .B(B),
        .op(op),
        .result(result),
        .C(C),
        .Z(Z)
    );

    integer i;
    initial
        begin
            $dumpfile("alu_tb.vcd");
            $dumpvars(0,alu_tb);
            $monitor("At time %t \n\t A = 0x%h, \n\t B = 0x%h, \n\t op = %b, \n\t result =  0x%h, \n\t C = %b, \n\t Z = %b", $time, A, B, op, result, C, Z);

            B = 34000;
            A = 35000;
            for (i = 0; i < 4; i = i + 1)
                begin
                    op = i[1:0];
                    #5;
                end

            B = 16'h23;
            A = 16'hC4;
            for (i = 0; i < 4; i = i + 1)
                begin
                    op = i[1:0];
                    #5;
                end

            $finish;
        end
endmodule