--------------------------------------------------------------------------------
-- Entity: alu_tb
-- Date:2015-11-24
-- Author: usuario
--
-- Description: Testbench para la ALU
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;

entity alu_tb is
end alu_tb;

architecture test of alu_tb is
    signal A: unsigned (7 downto 0) := "00000000";
    signal B: unsigned (7 downto 0) := "00000000";
    signal C: std_logic;
    signal Z: std_logic;
    signal op: unsigned (1 downto 0) := "00";
    signal result: unsigned (7 downto 0);
begin

    uut: entity work.alu(FromVerilog)
        port map(A, B, C, Z, op, result);

    stimulus: process is
    begin
    -- Valores iniciales
    A <= "00001000";
    B <= "00001101";
    -- Recorremos las operaciones
    for I in 0 to 3 loop
        wait for 10 ns;
        op <= op + 1;
    end loop;
    -- Cambio de valores
    A <= "00101000";
    B <= "11011000";
    -- Recorremos las operaciones
    for I in 0 to 3 loop
        wait for 10 ns;
        op <= op + 1;
    end loop;

    wait;

    end process stimulus;
end test;