/**************************************
* Module: alu
* Date:2015-11-14
* Author: usuario
*
* Description:
***************************************/
module  alu(A,B,op,result,C,Z);

// Definción de parámetros
parameter n_bits = 8;

// Entradas y salidas
input [n_bits-1:0] A, B;
output [n_bits-1:0] result;
input [1:0] op;
output C,Z;

// Operaciones
parameter add_op = 2'b00; // Suma
parameter and_op = 2'b01; // And
parameter or_op  = 2'b10; // Or
parameter com_op = 2'b11; // Complementar A

reg [n_bits-1:0] result;
reg C;

always@(A or B or op)
    case(op)
      add_op: {C, result} = A + B;
      and_op: {C, result} = {1'b0, A & B};
      or_op:  {C, result} = {1'b0, A | B};
      com_op: {C, result} = {1'b0 , ~A};
      default {C, result} = {n_bits+1{1'b0}};
    endcase

reg Z;
always@(result)
    if (result == 0)
        Z <= 1'b1;
    else
        Z <= 1'b0;

endmodule