module sync_ram_dualport
#(parameter data_width = 16,
  parameter addr_width = 32)
 (input clk_in, clk_out, we,
  input [addr_width - 1:0] addr_in,
  input [addr_width - 1:0] addr_out,
  input [data_width - 1:0] data_in,
  output reg [data_width - 1:0] data_out);

  reg [data_width - 1:0] mem [2^(addr_width -1):0];

  always @(posedge clk_in) begin
    if (we)mem[addr_in] <= data_in;
  end

  always @(posedge clk_out) begin
    data_out <= mem[addr_out];
  end

endmodule //sram2p