module fsm2
(input clk, reset, c,
 output reg [3:0] salida);

  reg [1:0] status;  // estado

always @(posedge clk or negedge reset)
  if (!reset) begin
    status <= 0;
    salida <= 3'b010;
  end
  else
    case (status)
      0: if (c) begin
           status <= 1;
           salida <= 3'b100;
         end
      1: begin
           status <= 2;
           salida <= 3'b111;
         end
      2: if (c) begin
           status <= 1;
           salida <= 3'b100;
         end
         else begin
            status <= 0;
            salida <= 3'b010;
         end
    endcase
endmodule // fsm2