module fsm1
(input clk, reset, c,
 output reg [1:0] status);

always @(posedge clk or negedge reset)
  if (!reset) status = 0;
  else
    case (status)
      0: if (c) status = 1;
      1: status = 2;
      2: if (c) status = 1;
         else status = 0;
    endcase
endmodule // fsm1