-- This VHDL was converted from Verilog using the
-- Icarus Verilog VHDL Code Generator 0.9.7  (v0_9_7)

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;

-- Generated from Verilog module alu (alu.v:8)
entity alu is
  port (
    A : in unsigned(7 downto 0);
    B : in unsigned(7 downto 0);
    C : out std_logic;
    Z : out std_logic;
    op : in unsigned(1 downto 0);
    result : out unsigned(7 downto 0)
  );
end entity;

-- Generated from Verilog module alu (alu.v:8)
architecture FromVerilog of alu is
  signal C_Reg : std_logic := '0';
  signal Z_Reg : std_logic := '0';
  signal result_Reg : unsigned(7 downto 0) := "00000000";
begin
  C <= C_Reg;
  Z <= Z_Reg;
  result <= result_Reg;

  -- Generated from always process in alu (alu.v:28)
  process (op, B, A) is
    variable Verilog_Assign_Tmp_0 : unsigned(8 downto 0);
    variable Verilog_Assign_Tmp_1 : unsigned(8 downto 0);
    variable Verilog_Assign_Tmp_2 : unsigned(8 downto 0);
    variable Verilog_Assign_Tmp_3 : unsigned(8 downto 0);
    variable Verilog_Assign_Tmp_4 : unsigned(8 downto 0);
  begin
    case op is
      when "00" =>
        Verilog_Assign_Tmp_0 := (Resize(A, 9) + Resize(B, 9));
        result_Reg <= Verilog_Assign_Tmp_0(7 downto 0);
        C_Reg <= Verilog_Assign_Tmp_0(8);
      when "01" =>
        Verilog_Assign_Tmp_1 := ('0' & (A and B));
        result_Reg <= Verilog_Assign_Tmp_1(7 downto 0);
        C_Reg <= Verilog_Assign_Tmp_1(8);
      when "10" =>
        Verilog_Assign_Tmp_2 := ('0' & (A or B));
        result_Reg <= Verilog_Assign_Tmp_2(7 downto 0);
        C_Reg <= Verilog_Assign_Tmp_2(8);
      when "11" =>
        Verilog_Assign_Tmp_3 := ('0' & (not A));
        result_Reg <= Verilog_Assign_Tmp_3(7 downto 0);
        C_Reg <= Verilog_Assign_Tmp_3(8);
      when others =>
        Verilog_Assign_Tmp_4 := "000000000";
        result_Reg <= Verilog_Assign_Tmp_4(7 downto 0);
        C_Reg <= Verilog_Assign_Tmp_4(8);
    end case;
  end process;

  -- Generated from always process in alu (alu.v:38)
  process (result_Reg) is
  begin
    if (Resize(result_Reg, 9) = "000000000") then
      Z_Reg <= '1';
    else
      Z_Reg <= '0';
    end if;
  end process;
end architecture;